1. Technical Field
The present invention relates to a semiconductor device, a method of fabricating a semiconductor device, and a layout method of a semiconductor device. The present invention relates in particular to a semiconductor device provided with a decoupling capacitor, and method of fabricating a semiconductor device and semiconductor device layout method of the same.
2. Related Art
Decoupling capacitance is required in order to stabilize operation of a circuit of a semiconductor device, however gate capacitance and junction capacitance used in integrated circuits of a semiconductor device function as decoupling capacitance, and, since there is also parasitic capacitance present generated in lines connecting between elements, a degree of decoupling capacitance is secured.
However, due to demands due to improvements in miniaturization processing technology and lower power consumption in recent semiconductor devices, there is a tendency for the power source voltage of semiconductor devices to decrease, while the current consumption in semiconductor devices remains large due to the increasing scale of integrated circuits. There is a need to secure further decoupling capacitance when the power supply voltage is low, since sometimes there is a malfunction in circuit operation when, due to the operation current, the same level of voltage drop as previously occurs in power source lines.
There is a proposal for a semiconductor device to secure decoupling capacitance by provision of an extra cell(s) to give decoupling capacitance, separate from the basic cells to give elements to configure inverter circuits, NAND circuits, flip-flops and the like (see, for example, Japanese Patent Application Laid-Open (JP-A) No. 2007-299860.
However, there is a problem with the semiconductor device described in JP-A No. 2007-299860 in that the surface area of the semiconductor device is increased, due to provision of the extra cell(s), separate from the basic cells, in order to secure decoupling capacitance.